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-rw-r--r--4.5.2/gentoo/24_all_4.5.2_pr43653_clang_ICE.patch80
-rw-r--r--4.5.2/gentoo/README.history3
2 files changed, 83 insertions, 0 deletions
diff --git a/4.5.2/gentoo/24_all_4.5.2_pr43653_clang_ICE.patch b/4.5.2/gentoo/24_all_4.5.2_pr43653_clang_ICE.patch
new file mode 100644
index 0000000..d866366
--- /dev/null
+++ b/4.5.2/gentoo/24_all_4.5.2_pr43653_clang_ICE.patch
@@ -0,0 +1,80 @@
+Unrecognizable insn with -O1 -ftree-vectorize
+
+http://gcc.gnu.org/PR43653
+https://bugs.gentoo.org/322419
+
+--- gcc/config/i386/i386.c
++++ gcc/config/i386/i386.c
+@@ -25137,7 +25137,8 @@
+ {
+ /* QImode spills from non-QI registers require
+ intermediate register on 32bit targets. */
+- if (!in_p && mode == QImode && !TARGET_64BIT
++ if (!TARGET_64BIT
++ && !in_p && mode == QImode
+ && (rclass == GENERAL_REGS
+ || rclass == LEGACY_REGS
+ || rclass == INDEX_REGS))
+@@ -25157,6 +25158,45 @@
+ return Q_REGS;
+ }
+
++ /* This condition handles corner case where an expression involving
++ pointers gets vectorized. We're trying to use the address of a
++ stack slot as a vector initializer.
++
++ (set (reg:V2DI 74 [ vect_cst_.2 ])
++ (vec_duplicate:V2DI (reg/f:DI 20 frame)))
++
++ Eventually frame gets turned into sp+offset like this:
++
++ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
++ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
++ (const_int 392 [0x188]))))
++
++ That later gets turned into:
++
++ (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
++ (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
++ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
++
++ We'll have the following reload recorded:
++
++ Reload 0: reload_in (DI) =
++ (plus:DI (reg/f:DI 7 sp)
++ (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
++ reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
++ SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
++ reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
++ reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
++ reload_reg_rtx: (reg:V2DI 22 xmm1)
++
++ Which isn't going to work since SSE instructions can't handle scalar
++ additions. Returning GENERAL_REGS forces the addition into integer
++ register and reload can handle subsequent reloads without problems. */
++
++ if (in_p && GET_CODE (x) == PLUS
++ && SSE_CLASS_P (rclass)
++ && SCALAR_INT_MODE_P (mode))
++ return GENERAL_REGS;
++
+ return NO_REGS;
+ }
+
+--- gcc/testsuite/gcc.target/i386/pr43653.c
++++ gcc/testsuite/gcc.target/i386/pr43653.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O1 -ftree-vectorize -msse" } */
++
++typedef struct {} S;
++
++void *foo()
++{
++ S a[64], *p[64];
++ int i;
++
++ for (i = 0; i < 64; i++)
++ p[i] = &a[i];
++ return p[0];
++}
diff --git a/4.5.2/gentoo/README.history b/4.5.2/gentoo/README.history
index 9f1274d..96034c7 100644
--- a/4.5.2/gentoo/README.history
+++ b/4.5.2/gentoo/README.history
@@ -1,3 +1,6 @@
+1.2 pending
+ + 24_all_4.5.2_pr43653_clang_ICE.patch
+
1.1 13.02.2011
+ 22_all_4.6_pr45094_arm-dword-move.patch
+ 23_all_4.6_pr45886_ARM_PCS_VFP.patch