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* target-sh4: fix negcAurelien Jarno2011-02-041-2/+2
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 7026259f79ffc85ceaaaeee32df518ea96863ee4)
* target-sh4: update PTEH upon MMU exceptionAlexandre Courbot2011-01-261-0/+4
| | | | | | | | Update the PTEH register to contain the VPN at which an MMU exception occured as specified by the SH4 reference. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* sh4: implement missing mmaped TLB read functionsAurelien Jarno2011-01-262-0/+82
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* sh4: implement missing mmaped TLB write functionsAurelien Jarno2011-01-262-3/+67
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix index of address read error exceptionAlexandre Courbot2011-01-251-1/+1
| | | | | | | Exception index of address read error should be 0x0e0. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix TLB invalidation codeAlexandre Courbot2011-01-251-2/+2
| | | | | | | | In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and the ITLB left unchaged, probably because of some unfortunate copy/paste. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement negc using TCGAurelien Jarno2011-01-163-17/+15
| | | | | | | Using setcond it's now possible to generate a relatively short negc instruction in TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use rotl/rotr when possibleAurelien Jarno2011-01-161-5/+3
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: correct use of ! and &Aurelien Jarno2011-01-151-2/+2
| | | | | | | | Fix wrong usage of ! and & in MMU related functions. Thanks to Blue Swirl for reporting the issue. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use setcond when possibleAurelien Jarno2011-01-141-29/+27
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: log instructions start in TCG codeAurelien Jarno2011-01-141-0/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: simplify comparisons after a 'and' opAurelien Jarno2011-01-141-3/+3
| | | | | | | | When a TCG variable is anded with a value and the compared with the same value, we can simply invert the comparison and compare it with 0. The generated code is smaller. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix reset on r2dAurelien Jarno2011-01-142-18/+16
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: optimize exceptionsAurelien Jarno2011-01-142-15/+12
| | | | | | | As exception is not the normal path, don't bother saving PC, before raising one, instead rely on code retranslation to get the CPU state. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: add ftrv instructionAurelien Jarno2011-01-143-0/+38
| | | | | | | Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: add fipr instructionAurelien Jarno2011-01-143-0/+33
| | | | | | | Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement FPU exceptionsAurelien Jarno2011-01-141-22/+136
| | | | | | | | | | | FPU exception support where not implemented on SH4. Implement them by clearing the softfloat exceptions flags before an FP instruction (the SH4 FPU also clear them before an instruction), and calling a function to update the FPSCR register after an FP instruction. This function update the corresponding FPSCR bits (both flags and cumulative flags) and trigger exception if enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement flush-to-zeroAurelien Jarno2011-01-142-0/+2
| | | | | | | When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as zero. Enable the corresponding softfloat option when this bit is set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: define FPSCR constantsAurelien Jarno2011-01-143-9/+37
| | | | | | | Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use default-NaN modeAurelien Jarno2011-01-141-0/+1
| | | | | | | SH4 FPU doesn't propagate NaN, and instead always regenerate new ones. Enable the default-NaN mode by default. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix fpu disabled/illegal exceptionAurelien Jarno2011-01-111-10/+18
| | | | | | | | | | | Illegal instructions in a slot delay should generate a slot illegal instruction exception instead of an illegal instruction exception. The current PC should be saved before generating such an exception, but should not be corrected if in a delay slot, given it's already done in the exception handler do_interrupt(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: improve TLBAurelien Jarno2011-01-101-21/+44
| | | | | | | | | | | | | | | | | SH4 is using 16-bit instructions which means most of the constants are loaded through a constant pool at the end of the subroutine. The same memory page is therefore accessed in exec and read mode. With the current implementation, a QEMU TLB entry is set to read or read/write mode after an UTLB search and to exec mode after an ITLB search, which causes a lot of TLB exceptions to switch from read or read/write to exec and vice versa. This patch optimizes that by already setting the QEMU TLB entry in read or read/write mode when an UTLB entry is copied into ITLB (during an ITLB miss). This improve the emulation speed by about 14%. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement writes to mmaped ITLBAurelien Jarno2011-01-092-0/+21
| | | | | | | | | | | Some Linux kernels seems to implement ITLB/UTLB flushing through by writing all TLB entries through the memory mapped interface instead of writing one to MMUCR.TI. Implement memory mapped ITLB write interface so that such kernels can boot. This fixes https://bugs.launchpad.net/bugs/700774 . Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-302-2/+3
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: Add support for ldc & stc with sgrAlexandre Courbot2010-07-121-0/+2
| | | | | | | | | | | | | | | Add support for the following missing priviledged intructions: For SH4: - stc sgr, Rn - stc.l sgr, @-Rn For SH4A: - ldc Rm, sgr - ldc.l @Rm+, sgr Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: Split the LDST macro into 2 sub-macrosAlexandre Courbot2010-07-121-2/+6
| | | | | | | | | | | The LDST macro is used to generate ldc and stc instructions that work with a specific register. However, the SGR register only supports stc up to SH4A, which supports both stc and ldc. This patch creates two sub-macros named LD and ST that handle generating ldc and stc instructions separately, and redeclares LDST to use these sub-macro. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove exec-all.h inclusion from cpu.hPaolo Bonzini2010-07-031-1/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2010-07-032-6/+6
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: Remove duplicate CPU log.Richard Henderson2010-05-051-6/+0
| | | | | | | Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove TARGET_* defines from translate-all.cPaolo Bonzini2010-04-081-0/+2
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-183-5/+5
| | | | | | | | | When building with -DNDEBUG, assert(0) will not stop execution so it must not be used for abnormal termination. Use cpu_abort() when in CPU context, abort() otherwise. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Large page TLB flushPaul Brook2010-03-171-1/+2
| | | | | | | | | | | | | | | | | | QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Target specific usermode cleanupPaul Brook2010-03-121-0/+2
| | | | | | Disable various target specific code that is only relevant to system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Remove cpu_get_phys_page_debug from userspace emulationPaul Brook2010-03-121-5/+0
| | | | | | cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+3
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Fix incorrect exception_index useBlue Swirl2010-02-141-1/+1
| | | | | | | | | | env->exception_index should be cleared with -1, not 0. See also 821b19fe923ac49a24cdb4af902584fdd019cee6. Spotted by Igor Kovalenko. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: MMU: separate execute and read/write permissionsAurelien Jarno2010-02-091-21/+6
| | | | | | | | | On SH4, the ITLB and UTLB configurations are memory mapped, so loading ITLB entries from UTLB has to be simulated correctly. For that the QEMU TLB has to be handle the execute (ITLB) and read/write permissions (UTLB) seperately. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: fix store queue addressesAurelien Jarno2010-02-091-1/+1
| | | | | | The store queues are located from 0xe0000000 to 0xe3ffffff. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: remove dead codeAurelien Jarno2010-02-091-18/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: reduce the size of a TLB entryAurelien Jarno2010-02-091-12/+11
| | | | | | | Reduce the size of the TLB entry from 32 to 16 bytes, reorganising members and using a bit field. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: optimize UTLB accessesAurelien Jarno2010-02-091-24/+14
| | | | | | | | | | | | | | | With the current code, the QEMU TLB is setup to match the read/write mode of the MMU fault. This means when read access is done, the page is setup in read-only mode. When the page is later accessed in write mode, an MMU fault happened, and the page is switch in write-only mode. This flip-flop causes a lot of calls to the MMU code and slow down the emulation. This patch changes the MMU emulation, so that the QEMU TLB is setup to match the UTLB protection key. This impressively increase the speed of the emulation. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: fix ITLB priviledge checkAurelien Jarno2010-02-091-1/+1
| | | | | | | There is an ITLB access violation if SR_MD=0 (user mode) while the high bit of the protection key is 0 (priviledge mode). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: simplify call to tlb_set_page()Aurelien Jarno2010-02-091-6/+3
| | | | | | | tlb_set_page() doesn't need addresses with offset, but simply the page aligned addresses. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: fix mem_idx computationAurelien Jarno2010-02-091-1/+1
| | | | | | | | The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0 corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user mode (SR_MD = 0). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* sh7750: handle MMUCR TI bitAurelien Jarno2010-02-092-0/+20
| | | | | | | When the MMUCR TI bit is set, all the UTLB and ITLB entries should be flushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: minor optimisationsAurelien Jarno2010-02-081-26/+26
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* kill regs_to_env and env_to_regsPaolo Bonzini2010-01-191-10/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-012-4/+4
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-012-4/+4
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* Fix Sparse warnings about using plain integer as NULL pointerBlue Swirl2009-09-211-2/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>