diff options
| author |   Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2016-11-18 10:02:16 +0000 |
| commit | c2c4ff8d52a2cd3263a547b0384692498714aa1b (patch) | |
| tree | 2b85adf0b7eb999a0272cad8dde99c54118c3945 /opcodes/aarch64-opc-2.c | |
| parent | [AArch64] Add ARMv8.3 weaker release consistency load instructions (diff) | |
| download | binutils-gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.gz binutils-gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.tar.bz2 binutils-gdb-c2c4ff8d52a2cd3263a547b0384692498714aa1b.zip | |
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 110 |
1 files changed, 57 insertions, 53 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 935b7af67ce..e1729a87b73 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -90,6 +90,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"}, {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations"}, {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"}, {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"}, @@ -210,85 +213,86 @@ const struct aarch64_operand aarch64_operands[] = static const unsigned op_enum_table [] = { 0, - 860, - 861, - 862, + 863, + 864, 865, - 866, - 867, 868, 869, - 863, - 864, 870, 871, - 893, - 894, - 895, + 872, + 866, + 867, + 873, + 874, + 896, + 897, 898, - 899, - 900, 901, 902, - 896, - 897, 903, 904, - 952, - 953, - 954, + 905, + 899, + 900, + 906, + 907, 955, + 956, + 957, + 958, 12, - 627, - 628, - 1147, - 1149, - 1151, - 959, + 630, + 631, 1150, - 1148, - 311, - 615, - 626, + 1152, + 1154, + 962, + 1153, + 1151, + 312, + 618, + 629, + 628, + 960, 625, - 957, 622, - 619, - 611, - 610, - 617, - 618, + 614, + 613, + 620, 621, - 623, 624, - 967, - 655, + 626, + 627, + 970, 658, 661, - 656, + 664, 659, - 804, - 171, + 662, + 807, 172, 173, 174, - 507, - 744, - 380, - 382, - 404, - 406, - 1212, - 1217, - 1210, - 1209, - 1213, + 175, + 510, + 747, + 383, + 385, + 407, + 409, + 1215, 1220, - 1222, + 1213, + 1212, + 1216, 1223, - 1219, 1225, - 1224, + 1226, + 1222, + 1228, + 1227, + 129, }; /* Given the opcode enumerator OP, return the pointer to the corresponding |