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| author |   Jim Wilson <jimw@sifive.com> | 2018-08-30 13:23:12 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-08-30 13:23:12 -0700 |
| commit | 43135d3b15ce10a786704f9bb4736d834d6581a8 (patch) | |
| tree | 09a46598dd29db01cd479dfc5f23f29abf68f8cb /opcodes/riscv-dis.c | |
| parent | Skip elf/section14 test for h8300 targets (diff) | |
| download | binutils-gdb-43135d3b15ce10a786704f9bb4736d834d6581a8.tar.gz binutils-gdb-43135d3b15ce10a786704f9bb4736d834d6581a8.tar.bz2 binutils-gdb-43135d3b15ce10a786704f9bb4736d834d6581a8.zip | |
RISC-V: Allow instruction require more than one extension
2018-08-29 Kito Cheng <kito@andestech.com>
gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.
include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
Diffstat (limited to 'opcodes/riscv-dis.c')
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 5b29d62a8c4..890f1f8e697 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -430,7 +430,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) if (no_aliases && (op->pinfo & INSN_ALIAS)) continue; /* Is this instruction restricted to a certain value of XLEN? */ - if (isdigit (op->subset[0]) && atoi (op->subset) != xlen) + if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) continue; /* It's a match. */ |